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Inter-Integrated Circuit
Delay
Start Counting High Period
SCL1
SCL2
SCL
Internal Counter Reset
Figure 9-10. I 2 C clock synchronization
9.4.1.8
Handshaking
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold
the SCL low after completion of one byte transfer (nine bits). In such case, it halts the bus clock and forces
the master clock into wait states until the slave releases the SCL line.
9.4.1.9
Clock stretching
The clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. After
the master has driven SCL low, the slave can drive SCL low for the required period and then release it. If
the slave SCL low period is greater than the master SCL low period then the resulting SCL bus signal low
period is stretched.
9.4.2
10-bit address
For 10-bit addressing, 0x11110 is used for the first five bits of the first address byte. Various combinations
of read/write formats are possible within a transfer that includes 10-bit addressing.
9.4.2.1
Master-transmitter addresses a slave-receiver
The transfer direction is not changed (see Table 9-11 ). When a 10-bit address follows a START condition,
each slave compares the first seven bits of t h e first byte of the slave address (11110XX) with its own
address and tests whether the eighth bit (R/W direction bit) is 0. It is possible that more than one device
finds a match and generates an acknowledge (A1). Each slave that finds a match compares the eight bits
of the second byte of the slave address with its own address, but only one slave finds a match and generate
an acknowledge (A2). The matching slave remains addressed by the master until it receives a STOP
condition (P) or a repeated START condition (Sr) followed by a different slave address.
MMA955xL Intelligent, Motion-Sensing Platform Hardware Reference Manual, Rev. 1.0
Freescale Semiconductor, Inc.
171
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